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rev. 0.3 9/10 copyright ? 2010 by silicon laboratories si5355 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5355 a ny -f requency 1?200 mh z q uad f requency 8-o utput c lock g enerator features applications description the si5355 is a highly flexible clock generator capable of synthesizing four completely non-integer related frequencies up to 200 mhz. the device has four banks of outputs with each bank suppo rting two cmos outputs at the same frequency. using silicon laboratories' pa tented multisynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of configuration, enabling the replacement of multiple clock ics and crystal oscillators with a single device. th rough a flexible web configuration utility called clockbuilder? ( www.silabs.com/clockbuilder ), factory-customized pin- controlled si5355 devices are available in two weeks without minimum order quantity restrictions. the si5355 supports up to three independent, pin-selectable device configurations, enabling one device to replace three separate clock ics. functional block diagram ? generates any frequency from 1 to 200 mhz on each of the 4 output banks ? guaranteed 0 ppm frequency synthesis error for any combination of frequencies ? 25 or 27 mhz xtal or 5?200 mhz input clk ? eight cmos clock outputs ? five programmable control pins (output enable, frequency select, reset) ? separate oeb pins to disable individual banks or all outputs ? loss of signal output ? low 50 ps (typ) pk-pk period jitter ? phase jitter: 2 ps rms 12 khz?20 mhz ? excellent psrr performance eliminates need for external power supply filtering ? low power: 45 ma ? core vdd: 1.8, 2.5, or 3.3 v ? separate vddo for each bank of outputs: 1.8, 2.5, or 3.3 v ? small size: 4x4 mm 24-qfn ? industrial temperature range: ?40 to +85 c ? custom versions available using clockbuilder? web utility ? samples available in 2 weeks ? printers ? audio/video ? networking ? communications ? storage ? switches/routers ? computing ? servers ? oc-3/oc-12 line cards ordering information: see page 20. pin assignments xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23
si5355 2 rev. 0.3
si5355 rev. 0.3 3 t able of c ontents 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2. breakthrough multisynth technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3. input and output frequen cy configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4. multi-function control input s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5. output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3.6. frequency select/device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7. loss-of-signal alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.8. cmos output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9. jitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10. power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11. clockbuilder web- customization utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. pin descriptions?si5355 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
si5355 4 rev. 0.3 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units ambient temperature t a ?40 ? 85 o c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 1.71 1.8 1.98 output buffer supply voltage v ddo 1.71 ? 3.63 v note: all minimum and maximum specifications are guar anteed and apply across the recommended operating conditions. typical values apply at nominal supply vo ltages and an operating temperature of 25 c unless otherwise noted. table 2. absolute maximum ratings 1 parameter symbol rating units supply voltage range v dd ?0.5 to 3.8 v input voltage range (all pi ns except pins 1,2,5,6) v i ?0.5 to 3.8 v input voltage range (pins 1,2,5,6) v i2 ?0.5 to 1.4 v output voltage range v o ?0.5 to (v dd + 0.3) v storage temperature range t s ?55 to +150 o c esd tolerance hbm 2.5 kv cdm 550 v mm 175 v latch-up tolerance lu jesd78 compliant soldering temperature (pb-free profile) 2 t peak 260 o c notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specif ied in the operational sections of this data sheet. exposure to maximum rating cond itions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020c.
si5355 rev. 0.3 5 table 3. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units current consumption i dd 100 mhz on all outputs, 25 mhz refclk ?4560ma high level input voltage v ih clkin, p1, p2, p3 0.8 x v dd ?3.63 v oeb, pins (p4, p5) 0.85 ? 1.2 v low level input voltage v il clkin, p1, p2, p3 ?0.2 ? 0.2 x v dd v p4,p5 ? ? 0.3 v clock output high level output voltage v oh pins: clk0-7 i oh =?4 ma v ddo ? 0.3 ? ? v clock output low level out- put voltage v ol pins: clk0-7 i oh =+4ma ??0.3v los low level output voltage v ollos pin: los i oh =+3ma 0?0.4v pn input resistance r in 20 ? ? k ?
si5355 6 rev. 0.3 table 4. ac characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units input clock clock input frequency f in 5?200mhz clock input rise/fall time t r /t f 20 to 80% v dd ?? 2 ns clock input duty cycle dc < 2 ns tr/tf 40 ? 60 % clock input capacitance c in ?2? pf output clocks clock output frequency f o 1?200mhz clock output frequency synthesis resolution f res see "3.3. input and output frequency configuration" on page 11 ? ? 0 ppm output load capacitance c l ?15? pf clock output rise/fall time t r /t f 20 to 80% v dd , c l =15pf ??1.7 ns clock output rise/fall time t r /t f 20 to 80% v dd , c l =2pf ? 0.45 0.85 ns clock output duty cycle dc 45 50 55 % powerup time t pu por to output clock valid ? ? 2 ms output enable time t oe ??10 s output transition time t trans after falling edge of reset ? ? 2 ms reset minimum pulse width t reset ??200 ns output-output skew t skew outputs at same frequency, f out > 5 mhz ?150 ? +150 ps clkin loss of signal assert time t los ?2.6 5 s clkin loss of signal deassert time t los_b 0.01 0.2 1 s por to output clock valid t rdy ?? 2 ms period jitter j ppkpk 10000 cycles ? 50 75 ps pk-pk cycle-cycle jitter note: measured in accordance to jedec standard 65. j ccpk 10000 cycles ? 40 70 ps pk phase jitter j ph 12 khz to 20 mhz ? 2 ? ps rms pll loop bandwidth f bw ?1.6? mhz
si5355 rev. 0.3 7 table 5. crystal specifications parameter symbol test condition min typ max units crystal frequency f xtal option 1 ? 25 ? mhz option 2 ? 27 ? mhz load capacitance (on-chip differential) c l 11 12 13 pf crystal output capacitance c o < 30 mhz, esr < 90 ? ??5pf max drive level d l 100 ? ? w table 6. thermal characteristics parameter symbol test condition value units thermal resistance junction to ambient theta ja still air 37 o c/w thermal resistance junction to case theta jc still air 25 o c/w
si5355 8 rev. 0.3 2. typical application circuit programmable input pins ethernet phy si5355 4-port ethernet switch/router 33/66 mhz 125 mhz x x ethernet phy ethernet phy ethernet phy 22 18 14 10 9 25 mhz clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 ethernet switch mcu/ processor 1 2 4 25 mhz xtal xa xb clkin 25 mhz 25 mhz 25 mhz 8 los 3 5 12 19 6 p1 p2 p3 p4 p5 loss of signal rse rsh rsh rse gnd gnd pad 23 23 pad +3.3v 1k 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) note: see section 3.1 for information on selecting rse and rsh. si5355 laser printer x x 22 18 14 10 9 clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 1 2 4 25 mhz xtal xa xb clkin 23 gnd gnd pad 23 pad processor 125 mhz ddr memory touchscreen controller usb controller print head paper tray lcd screen key pad 48 mhz 66/100 mhz ethernet phy 35.788 mhz x x los p1 p2 p3 p4 p5 programmable input pins 8 3 5 12 19 6 loss of signal rse rsh rsh rse +3.3v 1k 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) note: see section 3.1 for information on selecting rse and rsh.
si5355 rev. 0.3 9 3. functional description figure 1. si5355 functional block diagram 3.1. input configuration the si5355 input can be driven from either an external cr ystal or a reference clock. reference selection is made when the device configuration is specified using the clockbuilder ? web-based utility available at www.silabs.com/ clockbuilder . if the crystal input option is used, the si5355 opera tes as a free-running clock generator. in this mode of operation the device requires a low-cost 25 or 27 mhz fundamental mode crystal connected across xa and xb as shown in figure 2. given the si53 55?s frequency flexibility, the same 25 or 27 mhz crystal can be reused to generate any combination of output frequencies. cu stom frequency crystals are not required. the si5355 integrates the crystal load capacitors on-chip to reduce external component count. the crystal should be placed very close to the device to minimize stray capacitance. to ensure stable oscillation, the re commended crystal specifications provided in table 5 on page 7 must be followed. see an360 for additional details regarding crystal recommendations. figure 2. connecting an xtal to the si5355 for synchronous timing applications, the si5355 can lock to a 5 to 200 mhz cmos reference clock. a typical interface circuit is shown in figure 3. a series terminatio n resistor matching the driver?s output impedance to the impedance of the transmission line is recommended to reduce reflections. figure 3. interfacing cmos reference clocks to the si5355 xb xa xtal si5355 clkin 50 rs si5355
si5355 10 rev. 0.3 control input signals to p4 and p5 cannot exceed 1.2 v, yet also must meet the v oh and v ol specifications outlined in table 3 on page 5. when these inputs are driv en from cmos sources, a resistive attenuator as shown in the typical application circuits must be used. suggeste d standard 1% resistor values for rse and rsh are show in table 7. 3.2. breakthrough multisynth technology next-generation timing architectures require a wide ra nge of frequencies which are often non-integer related. traditional clock architectures address this by using a co mbination of single pll ics, 4-pll ics and discrete xos, often at the expense of bom comple xity and power. the si5355 uses pa tented multisynth technology to dramatically simplify timing architectu res by integrating the fre quency synthesis capability of 4 phase-locked loops (plls) in a single device, greatly minimizing size and powe r requirements versus traditional solutions. based on a fractional-n pll, the heart of the architecture is a lo w phase noise, high-frequency vco. the vco supplies a high frequency output clock to the multisynth block on each of the four independent output paths. each multisynth operates as a high -speed fractional divider with s ilicon laboratories' pr oprietary phase error correction to divide down the vco clock to the required output frequency with very low jitter. the first stage of the multisynth architecture is a fracti onal-n divider which switches seamlessly between the two closest integer divider values to pr oduce the exact output clock frequency with 0 ppm error. to eliminate phase error generated by this process, multisynth calculates the relative phase difference between the clock produced by the fractional-n divider and the desired output clock an d dynamically adjusts the phase to match the ideal clock waveform. this novel approach makes it possible to generat e any output clock frequency without sacrificing jitter performance. based on this architecture, the output of each multisynth can produce any frequency from 1 to 200 mhz. figure 4. silicon labs' multisynth technology table 7. 1% resistor values cmos level rse ( ? )rsh ( ? ) 1.8 v 1000 1580 2.5 v 1960 1580 3.3 v 3090 1580 fractional-n divider phase adjust phase error calculator divider select (div1, div2) f vco f out multisynth
si5355 rev. 0.3 11 3.3. input and output frequency configuration the si5355 utilizes a single pll-based ar chitecture, four independent multisyn th fractional output dividers, and a multisynth fractional feedback divider such that a single device provides the cl ock generation capability of 4 independent plls. unlike competitive multi-pll solution s, the si5355 can generate four unique non-integer related output frequencies with 0 ppm frequency error for an y combination of output frequencies. in addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between frequency configurations. the si5355 frequency configuration is set when the device configuration is specifie d using the clockbuilder web- based utility available at www.silabs.com/clockbuilder . any combination of output frequencies ranging from 1 to 200 mhz can be configured on each of the device outp uts. up to three unique device configurations can be specified in a single device, enabling the si5355 to replace 3 different clock generators. the following equation governs how the output frequency is calculated. where f in is the reference frequency, n is th e multisynth feedback divider value, p is the reference divider value, m i is the multisynth output divider value and f out is the resulting output frequency. the multisynth output and feedback dividers are fractional dividers expressed in term s of an integer and a fraction. the integer portion has 10-bit resolution and the fractional portion has 30-bit re solution in both the numerator and denominator, meaning that, for all practical purposes, any output frequency ca n be defined exactly from th e input frequency with exact (0 ppm) frequency synthesis error. 3.4. multi-function control inputs the si5355 supports 5 user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the functions listed below. the pinout of each device is customized using the clockbuilder ut ility. this enables the device to be custom tailored to a specific application. each of the different functions is described in further detail below. pin function description assignable pin name oeb_all output enable all. all outputs enabled when low. p1, p2, p3, p4, or p5 oeb_01 output enable bank a. clk0/1 enabled when low. p1, p2, p3, p4, or p5 oeb_23 output enable bank b. clk2/3 enabled when low. p1, p2, p3, p4, or p5 oeb_45 output enable bank c. clk4/5 enabled when low. p1, p2, p3, p4, or p5 oeb_67 output enable bank d. clk6/7 enabled when low. p1, p2, p3, p4, or p5 fs0 frequency select. selects active device fre quency plan from factory- configured profiles. p1, p2, or p3 fs1 frequency select. selects active device fre quency plan from factory- configured profiles. p1, p2, or p3 reset reset. device reset required to c hange fs[1:0] pin setting. p1, p2, p3, p4, or p5 f out f in n ? pm i ? ----------------- =
si5355 12 rev. 0.3 3.5. output enable each of the device?s four banks of cmos clock output s can be individually disabled using oeb_01, oeb_23, oeb_45 and oeb_67, respectively. alternatively, all clock outputs can be disabled using the master output enable oeb_all. when a si5355 clock ou tput bank is disabled, both outputs are dr iven to an active low state. when one or more banks of clock outputs are enabled or disabled, clock start and stop transitions are handled glitchlessly. 3.6. frequency select/device reset the device frequency plan is customized using the clockbu ilder web utility. the si5355 optionally supports up to three unique, pin-selectable configurations per device, e nabling one device to replace up to three separate clock ics. to select a particular frequency plan, set the fs pins as outlined below: for custom si5355 devices configured to support 2 fr equency plans, the fs pin should be set as follows: for custom si5355 devices configured to support 3 freque ncy plans, the fs[1:0] pins should be set as follows: i f a change is made to the fs[1:0] pin settings, the devi ce reset pin (reset) must be held high for the minimum pulse width specified in table 4 on page 6 to change the device configuration. the output clocks will be momentarily squelched until the device begi ns operation with the new frequency plan. the corresponding input/output frequency configuration (p rofiles) for a custom si5355 device can be looked up using the clockbuilder web-based utility. 3.7. loss-of-signal alarm the si5355 supports a loss of signal (los) output indica tor for monitoring the condition of the crystal/clock reference input. the los condition occurs when there is no input clock to the device. when an input clock is removed, the los pin will assert and the output clocks may drift up to 5%. when the input clock with an appropriate frequency is reapplied, the los pin will de-assert. fs profile 01 12 fs[1:0] profile 00 reserved 01 1 10 2 11 3 los output state description 0 no loss of signal 1 loss of signal present
si5355 rev. 0.3 13 3.8. cmos output drivers the si5355 has 4 banks of outputs with each bank compri sed of 2 clocks for a total of 8 cmos outputs per device. each of the output banks can operate from a differen t vddo supply (1.8 v, 2.5 v, 3.3 v), simplifying usage in mixed supply applications. all clock outputs between 1 and 200 mhz are in-phase to within 150 ps. when an output bank is disabled using any of the oeb functions, the clock outputs are stopped low. the cmos output driver has a controlled impedance in the range of 42 to 50 ??? which includes an internal 22 ? series resistor. an external series resistor is not needed when driving 50 ? traces. if higher impedance traces are used then a series resistor may be added. a typical configuration is shown in figure 5. figure 5. cmos output driver configuration multisynth bank a +1.8v, +2.5v, +3.3v vddoa clk0 clk1 multisynth bank c +1.8v, +2.5v, +3.3v vddoc clk4 clk5 multisynth bank d +1.8v, +2.5v, +3.3v vddod clk6 clk7 multisynth bank b +1.8v, +2.5v, +3.3v vddob clk2 clk3 pll 50 50 50 50 50 50 50 50 si5356
si5355 14 rev. 0.3 3.9. jitter performance the si5355 provides consistently low jitter for any combi nation of output frequencies. the device leverages a low phase noise single pll architecture and silicon labora tories? patented multisynth fractional output divider technology to deliver period jitter less than 50 ps pk-pk (t yp) for any output frequency plan. this level of jitter performance is guaranteed across process, temperature, a nd voltage. the si5355 provides superior performance to conventional multi-pll solutions which may suffer from degraded jitter performance depending on frequency plan and the number of active plls. 3.10. power supply considerations the si5355 has 2 core supply voltage pins (v dd ) and 4 clock output bank supply voltage pins (v ddoa ?v ddod ), enabling the device to be used in mixed supply applicatio ns. the si5355 does not require ferrite beads for power supply filtering. the device has ext ensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter. figure 6 shows t hat the additive jitter created when a si gnificant amount of noise is applied to the device power supply is very small. figure 6. peak-to-peak additive jitter from 100 mv sine wave on supply 3.11. clockbuilder we b-customization utility clockbuilder is a web-ba sed utility available at www.silabs.com/clockbuilder that allows hardware designers to tailor the si5355?s flexible clock architecture to meet an y application-specific requirements and order custom clock samples. through a simple point-and-click interface, users can specify any combination of input frequency and output frequencies and generate a custom part number fo r each application-spec ific configuration. in addition to creating part numbers, this utility can be used to order samples and place production orders. there are no minimum order quantity restrictions. clockbuilder enables mass customization of clock generators. this allo ws a broader range of applications to take advantage of using application-specific pin controlled clocks, simplifying design wh ile eliminating the firmware development required by traditional i 2 c-programmable clock generators. based on silicon labs? patented multis ynth technology, the device pll output frequency is constant and all clock output frequencies are synthesized by the four multisynth fractional dividers. all pll parameters, including divider settings, vco frequency, loop bandwidth, charge pump curr ent, and phase margin are internally set by the device during the configuration process. this ensures optimized jitte r performance an d loop stability while simplifying design. 0 1 2 3 4 5 6 7 8 9 10 0.0001 0.001 0.01 0.1 1 modulation frequency (mhz) additive jitter (ps pk-pk) vddo vdd
si5355 rev. 0.3 15 4. pin descriptions?si5355 note: center pad must be tied to gnd for normal operation. table 8. si5355 pin descriptions pin # pin name i/o description 1xa i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if an input clock is used on pin 4, this pin should be tied to gnd. 2xb i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if an input clock is used on pin 4, this pin should be tied to gnd. 3p1 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_01, oeb_23, oeb_45, oeb_67, frequen cy select, or rese t) is user-selectable at time of configuration using the clockbuilder configuration utility. 4clkin i single-ended input clock. if a single-ended clock is used as the device frequency reference, connect it to this pin. this pin functions as a high-impedance inpu t for cmos clock signals. the input should be dc coupled. if a crystal is used as the device frequency reference, this pin should be tied to gnd. xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23
si5355 16 rev. 0.3 5p4 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_01, oeb_23, oeb_45, oeb_67, or reset) is user-selectable at time of configuration using the clockbuilder configuration utility. a resistor vo ltage divider is recommended when controlled by a signal greater than 1.2 v. see ?2. typical application circuit? for details. 6p5 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_01, oeb_23, oeb_45, oeb_67, or reset) is user-selectable at time of configuration using the clockbuilder configuration utility. a resistor vo ltage divider is recommended when controlled by a signal greater than 1.2 v. see ?2. typical application circuit? for details. 7vddvdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. 8loso loss of signal. this pin functions as an input clock loss of signal status pin. 0 = no loss of signal 1 = loss of signal present this pin is open drain and requires an external > 1k ? pullup resistor. 9clk7o output clock 7. cmos output clock. if unused, this pin must be left floating. 10 clk6 o output clock 6. cmos output clock. if unused, this pin must be left floating. 11 vddod vdd clock output bank d supply voltage. power supply for clock outputs 6 and 7. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk6/7 are not used, this pin must be tied to pin 7 and/or pin 24. 12 p2 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_01, oeb_23, oeb_45, oeb_67, frequency select, or reset) is user-selectable at time of configuration using the clockbuilder configuration utility 13 clk5 o output clock 5. cmos output clock. if unused, this pin must be left floating. 14 clk4 o output clock 4. cmos output clock. if unused, this pin must be left floating. 15 vddoc vdd clock output bank c supply voltage. power supply for clock outputs 4 and 5. may be operated from a 1.8, 2.5 or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk4/5 are not used, this pin must be tied to pin 7 and/or pin 24. 16 vddob vdd clock output bank b supply voltage. power supply for clock outputs 2 and 3. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk2/3 are not used, this pin must be tied to pin 7 and/or pin 24. 17 clk3 o output clock 3. cmos output clock. if unused, this pin must be left floating. table 8. si5355 pin descriptions (continued)
si5355 rev. 0.3 17 18 clk2 o output clock 2. cmos output clock. if unused, this pin must be left floating. 19 p3 i multi-function input. this pin functions as a multi-function input pin. the pin function (oeb_all, oeb_01, oeb_23, oeb_45, oeb_67, frequency select, or reset) is user-selectable at time of configuration using the clockbuilder configuration utility 20 vddoa vdd clock output bank a supply voltage. power supply for clock outputs 0 and 1. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk0/1 are not used, this pin must be tied to pin 7 and/or pin 24. 21 clk1 o output clock 1. cmos output clock. if unused, this pin must be left floating. 22 clk0 o output clock 0. cmos output clock. if unused, this pin must be left floating. 23 gnd gnd ground. must be connected to system ground. minimize the ground path impedance for optimal performance of the device. 24 vdd vdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. gnd pad gnd gnd ground pad. this is the large pad in the center of the package. see"6. recommended pcb layout" on page 19 for the pcb pad sizes and ground via requirements. device specifications cannot be guaranteed unless the ground pad is properly connected to a ground plane on the pcb. table 8. si5355 pin descriptions (continued)
si5355 18 rev. 0.3 5. package outline: 24-lead qfn figure 7. 24-lead quad flat no-lead (qfn) table 9. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.35 2.50 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the je dec/ipc j-std-020 specification for small body components.
si5355 rev. 0.3 19 6. recommended pcb layout table 10. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0.50 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. connect the center ground pad to a ground plane with no less than five vias. these 5 vias should have a length of no more than 20 mils to the ground plane. via drill size should be no smaller than 10 mils. a longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components.
si5355 20 rev. 0.3 7. ordering guide use the clockbuil der web-based utility available at www.silabs.com/clockbuilder to specify a unique si5355 device configuration. clockbuilder assigns a unique 5-digi t code for each unique device configuration and creates an orderable part number. the utility may also be used to or der samples, plac e production orders and look up existing part numbers. in addition, clockbuilder gener ates a data sheet addendum for each unique part number that summarizes the device input frequency, output fr equencies and other configur ation parameters for that specific part number. si5355a axxxxx g any-frequency 1?200 mhz quad frequency 8-output clock generator a = product revision xxxxx = 5-digit custom code assigned to each unique device configuration by clockbuilder m = rohs6, pb-free qfn m r r = tape & reel blank = tubes g = ?40 to +85 o c
si5355 rev. 0.3 21 d ocument c hange l ist revision 0.1 to revision 0.2 ? documentation updated to reflect clkin is on pin 4, not pin 3. revision 0.2 to revision 0.3 ? added cycle-cycle and phase jitter specifications to table 4 on page 6. ? changed period jitter specification from 100 ps to 75 ps pk-pk. ? added theta jc specification to table 6 on page 7. ? updated "2. typical application circuit" on page 8. ? added table 7 on page 10. ? clarified device operation during an input clock loss of signal. ? updated recommended pcb layout.
si5355 22 rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and clockbuilder are trademar ks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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